招财鞭炮搭建

PCIe 3.0

The Innosilicon PCIE3.0 PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the PHY Interface for PCIE3.0 Super-Speed standard from Intel. The PHY supports PCIE3.0(8Gb/s/5Gb/s/2.5Gb/s) physical layer specifications.


The PHY module includes a top level wrapper integrating both the Physical Media Attachment (PMA) layer, and the Physical Coding Sub-Block (PCS) layer.

KEY FEATURES:

  • Standard PHY interface enables multiple IP sources for PCI
  • Express Logical Layer and provides a target interface for PCI
  • Express PHY vendors.
  • Supports 2.5Gb/s only or 2.5Gb/s,5.0Gb/s and 8.0Gb/s serial data transmission rate
  • Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive PCI Express data
  • Allows integration of high speed components into a single func tional block as seen by the endpoint device designer.
  • Data and clock recovery from serial stream on the PCI Express bus
  • Holding registers to stage transmit and receive data
  • Supports direct disparity control for use in transmitting compliance pattern
  • 8b/10b encode/decode and error indication
  • 128b/130b encode/decode and error indication
  • Receiver detection
  • Beacon transmission and reception
  • Selectable Tx Margining, Tx De-emphasis and signal swing values
  • Receive Equalization training

INNOSILICON ADVANTAGES:

  • As with all Innosilicon IP, the focus is on silicon proven, fully certified solutions providing
  • Small size
  • Low power
  • High ATE coverage
  • Simple integration
  • Flexible customization

BLOCK DIAGRAM:

EXAMPLE APPLICATIONS:

告訴我們您的IP需求 我們將提供定制化方案,滿足您的所有需求!
招财鞭炮搭建 十一选五河北时时 福彩排列七今天开奖结果 北京赛pk10提示 福彩走势 天天捕鱼电玩城正版赢话费 江西时时外挂 极速赛车信誉公众号哪里找 乐游棋牌app旧版本下载 云南体彩时时彩开奖结果 江西快三开奖结果走势图一定牛 30选5今天开奖号 新时时三星组三 北京快3官网app 吉林省快三开奖查询结果